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FPD750SOT89
LOW NOISE HIGH LINEARITY PACKAGED PHEMT
FEATURES (1.85GHZ):
*
* * * * *
Datasheet 3.0
PACKAGE:
RoHS
25 dBm Output Power (P1dB)
18 dB Small-Signal Gain (SSG) 0.6 dB Noise Figure 39 dBm Output IP3 55% Power-Added Efficiency FPD750SOT89E: RoHS compliant (Directive 2002/95/EC)
GENERAL DESCRIPTION:
The FPD750SOT89 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT). It utilizes a 0.25 m x 750 m Schottky barrier Gate, defined by high-resolution stepperbased photolithography. The double recessed gate structure minimizes parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a range of bias conditions and i/p power levels.
TYPICAL APPLICATIONS:
* * * Drivers or output stages in PCS/Cellular base station transmitter amplifiers High intercept-point LNAs WLL and WLAN systems, and other types of wireless infrastructure systems.
ELECTRICAL SPECIFICATIONS:
PARAMETER
Power at 1dB Gain Compression Small-Signal Gain
SYMBOL
P1dB SSG
CONDITIONS
VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 50% IDSS
MIN
23 16.5
TYP
25 18
MAX
UNITS
dBm dB
Power-Added Efficiency
PAE
VDS = 5 V; IDS = 50% IDSS; POUT = P1dB
50
%
Noise Figure
NF
VDS = 5 V; IDS = 50% IDSS VDS = 5 V; IDS = 25% IDSS
0.8 0.6
1.0
dB
Output Third-Order Intercept Point (from 15 to 5 dB below P1dB)
IP3
VDS = 5V; IDS = 50% IDSS Matched for optimal power Matched for best IP3 36 38 39 185 230 375 200 1 0.7 12 12 1.0 16 16 83 15 1.3 280 mA mA mS A V V V C/W dBm
Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Thermal Resistance
IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD| RJC
VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -5 V VDS = 1.3 V; IDS = 0.75 mA IGS = 0.75 mA IGD = 0.75 mA
Note: TAMBIENT = 22C; RF specification measured at f = 1850 MHz using CW signal (except as noted) 1
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FPD750SOT89
Datasheet v3.0
ABSOLUTE MAXIMUM RATING :
PARAMETER
Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current 2 RF Input Power Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression Simultaneous Combination of Limits 3 PIN TCH TSTG PTOT Comp. Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions 2 or more Max. Limits 175mW 175C -55C to 150C 1.8W 5dB
1
SYMBOL
VDS VGS IDS IG
TEST CONDITIONS
-3V < VGS < +0V 0V < VDS < +8V For VDS < 2V Forward or reverse current
ABSOLUTE MAXIMUM
8V -3V IDSS 7.5mA
Notes: 1 TAmbient = 22C unless otherwise noted; exceeding any one of these absolute maximum ratings may cause permanent damage to the device 2 Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously 4 Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where PDC: DC Bias Power, PIN: RF Input Power, POUT: RF Output Power Total Power Dissipation to be de-rated as follows above 22C: PTOT= 1.8 - (0.012W/C) x TPACK where TPACK= source tab lead temperature above 22C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 65C carrier temperature: PTOT = 1.8W - (0.012 x (65 - 22)) = 1.28W
BIASING GUIDELINES:
* Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices. For standard class A operation, a 50% of IDSS bias point is recommended. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point. A class A/B Bias of 25-33% of IDSS to achieve better OIP3, and Noise Figure performance is suggested.
* *
2
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FPD750SOT89
Datasheet v3.0
FREQUENCY RESPONSE:
35 30
Biased @ 5V 50%IDSS
1.2
MSG
Biased @ 5V, 100mA
25 20 15 10
Noise Figure (dB)
S21
1 0.8 0.6 0.4 N.F. (dB) 0.2
Mag S21
&
MSG
5
0
0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
0.5 1.5 2.5 3.5 4.5 5.5 Frequency (GHz) 6.5 7.5
8
Frequency (GHz)
Note: Device tuned for minimum noise figure
TEMPERATURE RESPONSE:
Biased @ 5V,50%IDSS Data taken on Eval Board at 1.85GHz
Biased @ 5V, 33% IDSS Data taken on Eval board @ 1.85GHz
26.0 25.0 24.0 23.0 22.0 21.0 20.0 19.0 18.0 17.0 16.0
20.0 19.0
SSG (dB)
1.80 1.60
Noise Figure (dB)
P1dB (dBm)
18.0 17.0 16.0 15.0 14.0
0 10 20 30 40 50 60 70 80 -20 -10 90
Temperature (C)
1.40 1.20 1.00 0.80 0.60 0.40
0 10 20 30 40 50 60 70 80 -20 -10
Temperature (C)
N.F. (dB)
SSG (dB) P1dB (dBm)
5.7
0
Note: Data Taken on Evaluation board tuned for maximum power. Achievable noise figure is lower when optimized.
3
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90
FPD750SOT89
Datasheet v3.0
TYPICAL TUNED RF PERFORMANCE:
Power Transfer Characteristic VDS = 5V IDS = 50% IDSS at f = 1.85 GHz
26.0 3.50 25.5
Pout (dBm) Comp Point
Drain Efficiency and PAE
60.0%
60.0%
PAE Eff.
3.00 Gain Compression (dB) 2.50
50.0%
25.0 Output Power (dBm)
50.0% Drain Efficiency (%)
24.5 24.0 23.5 23.0 22.5 22.0 4 5 6 7 8 Input Power (dBm) 9 10 11 12
2.00 1.50 1.00 0.50
PAE (%)
40.0%
40.0%
30.0%
30.0%
20.0%
20.0%
0.00 -0.50
10.0% 1 3 5 7 Input Power (dBm) 9 11 10.0%
NOTE: Typical power and efficiency is shown above. The devices were biased nominally at VDS = 5V, IDS = 50% of IDSS, at a test frequency of 1.85 GHz. The test devices were tuned (input and output tuning) for maximum output power at 1dB gain compression.
Typical Intermodulation Performance VDS = 5V IDS = 50% IDSS at f = 1.85GHz
-23.00 20
Pout (dBm) 3rds (dBc)
18 Output Power (dBm)
-28.00
16 -33.00 14 -38.00 12
10 -7.1 -6.0 -5.0 -4.0 -3.0 -2.1 -1.0 0.0 1.0 1.9 Input Power (dBm)
-43.00
Note: pHEMT devices have enhanced intermodulation performance. This yields OIP3 values of about P1dB + 14dBm. This IMD enhancement is affected by the quiescent bias and the matching applied to the device.
DC IV Curves FPD750SOT89
0.30
0.25
0.20
0.15
0.10
VG=-1.50 VG=-1.25V VG=-1.00V VG=-0.75V VG=-0.50V VG=-0.25V VG=0V
0.05
Note: The recommended method for measuring IDSS, or any particular IDS, is to set the Drain-Source voltage (VDS) at 1.3V. This measurement point avoids the onset of spurious self-oscillation which would normally distort the current measurement (this effect has been filtered from the I-V curves presented above). Setting the VDS > 1.3V will generally cause errors in the current measurements, even in stabilized circuits.
Drain-Source Current (A)
0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Drain-Source Voltage (V)
4
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3rd Order IM Products (dBc)
Website: www.filtronic.com
FPD750SOT89
Datasheet v3.0
TYPICAL OUTPUT PLANE POWER CONTOURS (VDS = 5v, IDS = 50%IDSS):
FPD750SOT89 POWER CONTUORS 900MHz
0.6
Swp Max 151
2. 0
0.8
1.0
10.0
0.2
0.4
0.6
0.8
1.0
2.0
3.0
4.0
5.0
0
20dBm 21dBm
-3 .0
.4 -0
23dBm
22dBm
.0 -2
-0.6
Swp Min 1
-0.8
1850 MHz Contours swept with a constant input power, set so that optimum P1dB is achieved at the point of output match. Input (Source plane) s:
0.50 142.8 0.37 + j0.35 (normalized) 18.5 + j17.5
Nominal IP3 performance is obtained with this input plane match, and the output plane match as shown.
900 MHz Contours swept with a constant input power, set so that optimum P1dB is achieved at the point of output match. Input (Source plane) s: 0.79 36.9 1.0 + j 2.6(normalized) 50 + j130 Nominal IP3 performance is obtained with this input plane match, and the output plane match as shown.
TYPICAL SCATTERING PARAMETERS (50 SYSTEM):
FPD750SOT89 5V / 50%IDSS
6 0.
FPD750SOT89 5V / 50%IDSS
6 0.
Swp Max 8GHz
2. 0
-1.0
1.0
0. 8
0 .8
1.0
5 GHz
0. 4
6 GHz
4 GHz 3.5 GHz 3 GHz
0 .2
3 7 GHz
.0
2. 0
4.
0
5.0
10.0
6 GHz 5 GHz
7 GHz
10.0 2.0 5.0 4.0 3.0
10.0
2.0
4.0 5.0
0.2
0.4
0.6
0.8
1.0
3.0
0.2
0.4
0.6
0.8
0
2.5 GHz
-10. 0
0
4 GHz
3 GHz 2 GHz
- 0. 2
-10. 0
. -0
. -0
4
.0 -2
-0 .
-0 .8
-1.0
-0 .8
S11
5
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-1.0
Swp Min 0.5GHz
S22
-0 .
1 GHz
.0 -2
6
6
-3
4
1.5 GHz
Swp Min 0.5GHz
-5
-4
.0
.0
.0
-5
-4
.0
- 0.
2
2 GHz
1.0
1 GHz
-4.0
24dBm
3.
-5.0
-0.2
Swp Max 8GHz
-10.0
0. 4
0 3.
4.0
5.0 0.2
10.0
19dBm 25dBm
0. 4
0
4.
0 .2
0
0
5.
10.0
.0
-3 .0
FPD750SOT89
Datasheet v3.0
REFERENCE DESIGN (0.9GHZ):
FREQUENCY Gain P1dB OIP31 N.F. S11 S22 Vd Vg Id GHZ dB dBm dBm dB dB dB V V mA 0.9 23 23.5 35 0.6 -5 -20 5 -0.4 to -0.6 100
1. Measured at 10dBm per tone
Board Layout
Vg 33pF 0.01uF 20O Lg 33pF L1 C1 33pF 0.01uF Ld L2 33pF Vd
+ 1.0uF +
Q1
0.63"
C2
1.45"
Component Values
Component Lg Ld L1 L2 C1 Value 56nH 56nH 12nH 6.8nH 0.5pF Description LL1608 Toko chip inductor LL1608 Toko chip inductor LL1608 Toko chip inductor LL1608 Toko chip inductor ATC 600S chip capacitor
FPD750SOT89 EVAL Board -Vg Schematic 0.01uF @ 0.9GHz 33pF
Vd
1.0uF 0.01uF 33pF 56 nH L2 C2 33pF
RF OUT
20 Ohm 56 nH L1 C1
33pF
RF IN
C2 1.2pF ATC 600S chip capacitor Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on both sides
D.C. Blocking capacitors are ATC series 600S. A tantalum 1.0F is used at the drain terminal. All other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from Vishay is used on the gate D.C. bias line for stability.
6
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FPD750SOT89
Datasheet v3.0
REFERENCE DESIGN (1.85GHZ):
FREQUENCY Gain P1dB OIP31 N.F. S11 S22 Vd Vg Id GHZ dB dBm dBm dB dB dB V V mA 1.85 17.2 24 35 0.7 -5 -10 5 -0.4 to -0.6 100
1. Measured at 10dBm per tone
Board Layout
Vg 33pF 0.01uF 20O Lg 33pF L1 C1 33pF 0.01uF Ld L2 33pF Vd
+ 1.0uF +
Q1
0.63"
C2
1.45"
Component Values
Component Lg Ld L1 L2 C1 Value 27nH 27nH 6.8nH 1.8nH 2.7pF Description LL1608 Toko chip inductor LL1608 Toko chip inductor LL1005 Toko chip inductor LL1005 Toko chip inductor ATC 600S chip capacitor
FPD750SOT89 EVAL Board -Vg Schematic 0.01uF @ 1.85GHz 33pF
Vd
1.0uF 0.01uF 33pF 27 nH L2 C2 33pF
RF OUT
20 Ohm 27 nH
33pF
RF IN
C1
C2 0.5pF ATC 600S chip capacitor Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on both sides
L1
D.C. Blocking capacitors are ATC series 600S. A tantalum 1.0F is used at the drain terminal. All other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from Vishay is used on the gate D.C. bias line for stability.
7
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FPD750SOT89
Datasheet v3.0
REFERENCE DESIGN (2.4GHZ TO 2.6GHZ):
Frequency (GHz) SSG (dB) P1dB (dBm) OIP3 (dBm) N.F. (dB) S11 (dB) S22 (dB) VD (V) VG (V) ID (mA)
1
2.4 15.4 24.3 34.0 0.95 -5.0 -9.5
2.5 15.2 24.3 35.0 0.95 -5.5 -10.0 5 -0.4 to -0.6 100
2.6 15.0 24.4 34.0 1.0 -6.0 -10.0
1. Measured at 10dBm per tone
Board Layout
Vg 33pF 0.01uF 20O Lg 33pF L1 C1 33pF 0.01uF Ld Tab 33pF Vd
+ 1.0uF +
Q1
0.63"
C2
1.45"
Component Values
Component Lg Ld L1 C1 C2 Value 22nH 22nH 8.2nH 2.0pF 0.8pF Description LL1608 Toko chip inductor LL1608 Toko chip inductor LL1005 Toko chip inductor ATC 600S chip capacitor ATC 600S chip capacitor
FPD750SOT89 EVAL Board -Vg Schematic 0.01uF @2.4 to 2.6GHz 33pF
Vd
1.0uF 0.01uF 33pF 22 nH C2 33pF
RF OUT
20 Ohm 22 nH
33pF
RF IN
C1
Tab Copper tab (no component) Eval board material - 31mil thick FR4 with 1/2 Ounce Cu on both sides
L1
D.C. Blocking capacitors are ATC series 600S. A tantalum 1.0F is used at the drain terminal. All other capacitors are 0603 and 0805 standard chip capacitors. A 0603 size 20 Ohm Chip resistor from Vishay is used on the gate D.C. bias line for stability.
8
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FPD750SOT89
Datasheet v3.0
STATISTICAL SAMPLE OF RF PERFORMANCE:
Small Signal Gain
18000 16000 14000
Frequency
Noise Figure
6000 5000
Frequency
12000 10000 8000 6000 4000 2000 0
4000 3000 2000 1000 0
0.5 0.9 0.58 0.66 0.74 0.82 0.98 1.06 1.14 1.22 1.3
15
17
15.4
15.8
16.2
16.6
17.4
17.8
18.2
18.6
19
19.4
19.8
More
NF (dB)
SSG (dB)
Output Power at 1dB gain Compression
10000
10000 9000 8000 7000
Frequency
Output 3rd Order Intercept Point
Frequency
8000 6000 4000 2000 0
20 20.6 21.2 21.8 22.4 23 23.6 24.2 24.8
6000 5000 4000 3000 2000 1000 0
25 26 28 29 31 32 34 35 37 38 40
P1dB (dBm)
OIP3 - (dBm)
Note: The devices were tested by a high-speed automatic test system, in a matched circuit based on an Evaluation Board design. This circuit is a dual-bias single-pole low pass topology, and the devices were biased at VDS = 4.0V, IDS = 100mA, Test frequency = 2.0GHz.
9
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FPD750SOT89
Datasheet v3.0
S-PARAMETERS: BIASED @ 5V, 50%IDSS:
FREQ[GHz] 0.050 0.300 0.550 0.800 1.050 1.300 1.550 1.800 2.050 2.300 2.550 2.800 3.050 3.300 3.550 3.800 4.050 4.300 4.550 4.800 5.050 5.300 5.550 5.800 6.050 6.300 6.550 6.800 7.050 7.300 7.550 7.800 8.050 8.300 8.550 8.800 9.050 9.300 9.550 9.800 10.050 10.300 10.550 S11m 0.998 0.959 0.868 0.809 0.755 0.713 0.679 0.653 0.634 0.62 0.613 0.603 0.611 0.614 0.619 0.627 0.636 0.659 0.663 0.666 0.68 0.695 0.706 0.719 0.732 0.741 0.754 0.766 0.779 0.793 0.809 0.823 0.839 0.851 0.86 0.871 0.881 0.889 0.895 0.904 0.913 0.909 0.903 S11a -5.6 -30.9 -52.5 -72.3 -90.2 -106.5 -121.5 -135.6 -148.8 -161.8 -173.5 175.0 164.6 154.5 145.1 136.2 127.9 119.7 110.6 104.1 96.9 89.7 82.6 75.9 69.2 62.7 56.9 51.1 45.4 39.9 34.4 28.9 23.6 18.8 14.2 9.8 5.7 2.0 -1.5 -4.6 -8.3 -12.0 -15.2 S21m 19.465 16.931 15.126 13.452 12.024 10.762 9.707 8.828 8.080 7.441 6.890 6.407 5.948 5.557 5.194 4.873 4.594 4.345 4.138 3.892 3.690 3.511 3.342 3.190 3.041 2.898 2.766 2.634 2.507 2.387 2.267 2.151 2.036 1.925 1.825 1.728 1.640 1.563 1.494 1.433 1.384 1.323 1.264 S21a 172.4 154.5 137.7 124.3 112.1 101.4 91.8 82.7 74.1 66.0 58.1 50.2 43.0 35.7 28.7 21.9 15.4 8.8 1.8 -4.8 -11.0 -17.4 -23.7 -30.1 -36.5 -42.8 -49.1 -55.3 -61.6 -67.8 -73.9 -79.9 -85.7 -91.3 -96.7 -102.0 -106.9 -111.8 -116.6 -121.2 -126.5 -132.0 -136.8 S12m 0.003 0.016 0.028 0.038 0.046 0.052 0.057 0.062 0.066 0.069 0.073 0.076 0.078 0.080 0.082 0.084 0.085 0.086 0.089 0.090 0.091 0.092 0.093 0.094 0.095 0.096 0.096 0.095 0.095 0.095 0.093 0.092 0.091 0.089 0.087 0.084 0.083 0.082 0.081 0.080 0.078 0.075 0.074 S12a 94.4 77.5 64.7 55.2 47.2 40.7 35.1 29.2 24.3 19.4 14.9 10.5 6.0 2.2 -2.4 -6.0 -10.3 -13.3 -17.5 -21.4 -25.1 -29.2 -32.6 -36.8 -41.0 -45.1 -49.1 -53.0 -57.4 -61.4 -65.7 -70.0 -74.0 -78.3 -81.9 -85.5 -89.4 -93.9 -98.4 -101.8 -107.1 -111.9 -116.6 S22m 0.448 0.438 0.406 0.379 0.352 0.324 0.294 0.267 0.241 0.214 0.188 0.169 0.14 0.123 0.113 0.11 0.114 0.133 0.138 0.153 0.167 0.182 0.196 0.208 0.222 0.237 0.252 0.27 0.291 0.314 0.337 0.363 0.387 0.412 0.436 0.457 0.477 0.496 0.514 0.531 0.548 0.552 0.557 S22a -8.1 -20.6 -37.7 -51.8 -64.3 -74.4 -83.0 -91.1 -98.8 -106.3 -115.6 -125.9 -140.7 -156.6 -175.2 164.9 146.6 132.4 115.2 107.8 99.7 92.6 85.4 78.5 71.6 65.0 58.0 51.3 44.6 38.5 33.2 28.4 24.3 20.3 17.1 14.0 11.0 8.6 6.0 3.1 -0.1 -3.6 -6.7
10
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FPD750SOT89
Datasheet v3.0
PACKAGE OUTLINE:
(dimensions in millimeters - mm)
TAPE DIMENSIONS AND PART ORIENTATION:
FWYN
Also available with horizontal part orientation Hub diameter = 80mm Devices per reel = 1000
11
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FPD750SOT89
Datasheet v3.0
DEVICE FOOT PRINT:
The device has a MSL rating of Level 2. To determine this rating, preconditioning was performed to the device per, the Pb-free solder profile defined within IPC/JEDEC J-STD-020C, Moisture / Reflow sensitivity classification for non-hermatic solid state surface mount devices.
APPLICATION NOTES & DESIGN DATA:
Application Notes and design data including Sparameters, noise parameters and device model are available on request.
RELIABILITY:
Units in inches
NOTE: Drawing available on Website
A MTTF of 7.4 million hours at a channel temperature of 150C is achieved for the process used to manufacture this device.
PREFERRED ASSEMBLY INSTRUCTIONS:
This package is compatible with both lead free and leaded solder reflow processes as defined within IPC/JEDEC J-STD-020C. The maximum package temperature should not exceed 260C.
DISCLAIMERS:
This product is not designed for use in any space based or life sustaining/supporting equipment.
ORDERING INFORMATION:
PART NUMBER
FPD750SOT89
HANDLING PRECAUTIONS:
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing.
DESCRIPTION
Packaged pHEMT Lead free Packaged pHEMT RoHS Compliant Packaged pHEMT with
FPD750SOT89E
FPD750SOT89CE
enhanced passivation (Recommended for New Designs)
EB750SOT89(E)-BB EB750SOT89(E)-BA
0.9 GHz evaluation board 1.85 GHz evaluation board 2.0 GHz evaluation board 2.4 GHz evaluation board 2.6 GHz evaluation board 3.5 GHz evaluation board 5.0 - 5.75 GHz evaluation board
ESD/MSL RATING:
These devices should be treated as Class 1A (250-500 V) using the human body model as defined in JEDEC Standard No. 22-A114.
EB750SOT89(E)-BC EB750SOT89(E)-BE EB750SOT89(E)-BG EB750SOT89(E)-AH EB750SOT89(E)-AJ
12
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